Programmable logic devices (“PLDs”) are a well-known type of integrated circuit that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (“FPGA”), typically includes an array of programmable tiles. These programmable tiles can include, for example, input/output blocks (“IOBs”), configurable logic blocks (“CLBs”), dedicated random access memory blocks (“BRAMs”), multipliers, digital signal processing blocks (“DSPs”), processors, clock managers, delay lock loops (“DLLs”), and so forth. As used herein, “include” and “including” mean including without limitation.
Each programmable tile typically includes both programmable interconnect and programmable logic. The programmable interconnect typically includes a large number of interconnect lines of varying lengths interconnected by programmable interconnect points (“PIPs”). The programmable logic implements the logic of a user design using programmable elements that can include, for example, function generators, registers, arithmetic logic, and so forth.
The programmable interconnect and programmable logic are typically programmed by loading a stream of configuration data into internal configuration memory cells that define how the programmable elements are configured. The configuration data can be read from memory (e.g., from an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA.
Another type of PLD is the Complex Programmable Logic Device, or CPLD. A CPLD includes two or more “function blocks” connected together and to input/output (“I/O”) resources by an interconnect switch matrix. Each function block of the CPLD includes a two-level AND/OR structure similar to those used in Programmable Logic Arrays (“PLAs”) and Programmable Array Logic (“PAL”) devices. In CPLDs, configuration data is typically stored on-chip in non-volatile memory. In some CPLDs, configuration data is stored on-chip in non-volatile memory, then downloaded to volatile memory as part of an initial configuration (programming) sequence.
For all of these programmable logic devices (“PLDs”), the functionality of the device is controlled by data bits provided to the device for that purpose. The data bits can be stored in volatile memory (e.g., static memory cells, as in FPGAs and some CPLDs), in non-volatile memory (e.g., FLASH memory, as in some CPLDs), or in any other type of memory cell.
Other PLDs are programmed by applying a processing layer, such as a metal layer, that programmably interconnects the various elements on the device. These PLDs are known as mask programmable devices. PLDs can also be implemented in other ways, e.g., using fuse or antifuse technology. The terms “PLD” and “programmable logic device” include but are not limited to these exemplary devices, as well as encompassing devices that are only partially programmable. For example, one type of PLD includes a combination of hard-coded transistor logic and a programmable switch fabric that programmably interconnects the hard-coded transistor logic.
Application integrated circuits, whether stand alone circuits or embedded circuits, namely “application specific blocks”, conventionally include internal memory, such as, for example, internal random access memory. Conventionally, a secure system having such an application specific block with internal random access memory is cleaned of retained data before the system starts. This may be a time consuming process performed by software. However, in some instances it may not be possible for software to clean internal random access memory, whether mapped or unmapped memory. It should be understood that FPGA internal memory structures can all be cleared after reset.
It should further be understood that conventional ASIC blocks have built-in self-test blocks or engines for testing internal random access memory during a test mode, as is performed by a manufacturer of such ASIC block. More recently, “Intellectual Property” (“IP”) cores may be licensed from one company to another company to include in their ASIC or to be included in a system on chip (“SoC”). Conventionally, licensors of cores will allow for an internal random access memory interface to be extended for access for testing in a test mode. Not all licensed cores have built-in self-test (“BIST”) engines, and thus the ability to access a RAM interface directly facilitates such testing in a test mode.
Due to limitations of securing ASIC blocks, including one or more ASIC blocks of a system, with respect to potentially sensitive data still present in an internal RAM, it would be desirable and useful to provide a less time consuming and potentially more thorough “cleaning” of such data.